Processor Core Family Offers New Features and Memory Power Reductions Up to 30%

“In their first year, the Diamond Standard cores have far exceeded our expectations,” stated Chris Rowen, Tensilica’s President and CEO. “Our customers have told us they were looking for the high performance, low power and small size of the Diamond Standard processor family. So we decided to make the family even faster, even lower power and even smaller. The second generation of Diamond Standard processor cores demonstrate our commitment to continued leadership in processor cores across the full range of control, DSP and media applications.”



The second generation Diamond Standard processors include three significant enhancements. First, the arithmetic capabilities of the controllers were significantly enhanced, reducing the need for external DSPs. An integer divider was added to the Diamond controllers (Diamond108Mini, Diamond 212GP, Diamond 232L, and Diamond 570T). This hardware divider significantly improves the performance of these processors on complex arithmetic applications like GPS, automotive applications, motor control, and engine control. A 32x32 single-cycle, pipelined multiplier has been added to the Diamond 108Mini, Diamond 212GP, and Diamond 232L processors, thereby improving the performance of these processors on common DSP algorithms (the Diamond 570T already had a multiplier).



Second, edge-triggered interrupts were added to all Diamond Standard processors, easing system design and giving faster interrupt response than level-triggered interrupts. Now, all Diamond Standard processors are available with up to 22 interrupts and 6 priority levels.



Third, Tensilica added support for relocatable exception vectors, which enables customers to change the memory location of exception handlers in software post-silicon. This gives more flexibility to the designer and eases system design.



Tensilica made several changes that allow power on the memory interfaces to be reduced by up to 30%. One of the biggest changes included memory system optimizations that leave local data memories turned off for longer periods of time without negatively impacting performance. Also, Tensilica designed in additional power-down modes, including external power-down of the trace port control and on-chip debug modules, lowering overall system power.



“Low power is sometimes the biggest concern for SOC designers as they evaluate processor cores,” added Rowen. “We are committed to continue to offer the industry’s best mix of low power and high performance in our cores.”







Tensilica now offers an optional AMBA AXI bridge in addition to the AMBA® AHB-lite that has been available to Diamond Standard processor customers. These AHB and AXI bridges enable designers to easily integrate Diamond Standard cores into AMBA-based SOCs. All Tensilica Diamond Series controller and DSP cores are available with the native high-performance Tensilica PIF processor interface that is suitable for bridging to any on-chip bus (e.g. OCP, CoreConnect), or with an AMBA AXI or AHB-Lite interface. SOC designers therefore can choose any common on-chip bus and leverage existing infrastructure and peripheral component sets.