Silicon-proven 3nm, 24Gbps UCIe IP subsystem

Built on TSMC’s advanced Chip-on-Wafer-on-Substrate (CoWoS) packaging technology, this solution marks a significant breakthrough in high-performance connectivity for technology infrastructure.

Developed in collaboration with TSMC, the complete PHY and controller subsystem is designed to address the demands of hyperscale data centres, high-performance computing (HPC), and AI applications. Leveraging TSMC’s CoWoS 2.5D silicon-interposer-based packaging, the subsystem delivers a high bandwidth density of 8 Tbps/mm while optimising I/O complexity, power consumption, and latency.

The subsystem supports a wide range of industry protocols, including PCIe, CXL, AXI-4, AXI-S, CXS, and CHI, ensuring compatibility across the evolving chiplet ecosystem. Additionally, it includes live per-lane health monitoring to enhance system reliability and operates at 24Gbps, meeting the high bandwidth demands of advanced D2D connectivity.

Alphawave Semi's UCIe IP subsystem has undergone extensive silicon characterisation with TSMC, validating its performance against UCIe standards and specifications under varying process, voltage, and temperature conditions. Key elements, such as D2D link margin, TXIO, and RXIO loopback margins, have been successfully tested, affirming its readiness for integration into customer system-on-chip (SoC) designs aimed at next-generation HPC and AI applications.

Mohit Gupta, Senior Vice President and General Manager of Custom Silicon and IP at Alphawave Semi, commented on the significance of this achievement: “Achieving successful silicon validation of 3nm 24 Gbps UCIe subsystem with TSMC’s advanced packaging is a significant milestone for Alphawave Semi and underscores the company’s expertise in utilising the TSMC 3DFabric ecosystem to deliver top-tier connectivity solutions.”

“Our recent collaboration with Alphawave Semi exemplifies how we collaborate with our Open Innovation Platform (OIP) ecosystem partners to enable significant advancements in packaging, meeting the increasing demands in AI and HPC applications,” said Dan Kochpatcharin, Head of Ecosystem and Alliance Management Division at TSMC. “We will continue our partnership with Alphawave Semi to advance the 3D IC design ecosystem to empower faster and power-efficient semiconductor designs.”

Complying with the latest UCIe Specification Rev 2.0, Alphawave Semi’s UCIe IP subsystem includes comprehensive testability features such as JTAG, Built-In Self-Test (BIST), Design-for-Test (DFT), and Known Good Die (KGD) capabilities, ensuring robust performance and ease of integration.

This release follows Alphawave Semi’s previous announcements regarding its 3nm UCIe IP subsystem, including the February 2024 announcement of the silicon-proven standard packaging version and the June release of the industry’s first multi-protocol chiplet. The availability of the 3nm 24Gbps UCIe IP subsystem with TSMC’s CoWoS packaging further solidifies Alphawave Semi's leadership in the high-performance connectivity space.