Challenges in ASIC Design for IoT to be presented by Cortus

Drawing on their experience with customers in the IoT area they will share the typical challenges that are faced when implementing IoT solutions. From the obvious low power requirements to the less obvious impact of code density but also including the various, sometimes contradictory, aspects of security.

“This gives us a great opportunity to share our experience with the challenges that our customers face when developing IoT solutions.” said Michael Chapman President and CEO of Cortus. “Sebastien Ternat and David Kerr-Munslow both have wide experience helping our customers and I am delighted that they will be able to share with this wider audience”.

IoT has become a key market. Many companies are creating ASIC and single chip solutions for their IoT projects and are faced with a combination of challenges that are not generally found together in other designs. Many of Cortus' processor cores answer these challenges and are used in deployed IoT products.

The Cortus family of APS processors starts with the world’s smallest 32 bit core, the APS1, and offers growing complexity up to the floating point FPS26 solution, including some cores that implement the RISC-V ISA. All cores interface to Cortus’ extensive IP portfolio, including caches, busses, bridges, peripherals such as Ethernet 10/100 MAC or USB. Most also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.

The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium uC/OSII & Micrium uC/OSIII and TargetOS.

To date over 1.9 billion devices have been manufactured containing Cortus processor cores, many of them in security conscious, power constrained systems.