Yokogawa Achieves 5X Faster Programmable Logic Controller Performance With Synopsys' Processor Designer

Our new PLC FA-M3V has achieved the fastest performance we've ever seen with our latest 'Vitesse Engine' core customized for ladder language program processing, said Hirofumi Okamoto, group leader of the PLC Development Division, Yokogawa Electric Corporation. With Processor Designer, we were able to develop this ultra-high performance processor using significantly less time and effort than we originally planned.

Yokogawa achieved their improvements in performance and time savings by leveraging Processor Designer's profiling capability to explore and optimize the processor's architecture. These optimizations enabled Yokogawa to meet their target ladder program processing performance goal of 3.75nSec/instruction – 5X faster than previous versions. By optimizing the LISA language input specification and hence the resulting RTL code, the design team also reduced power, gate count and total system development time en route to a successful tape-out.

Processor Designer dramatically accelerates the design of both application-specific processors and configurable accelerators through automated software development tools, RTL and ISS generation from a single, high-level specification. These application-specific processors and configurable accelerators are increasingly essential to support the convergence of multiple functionalities all on a single system-on-chip (SoC). Processor Designer is used to develop a wide range of processor architectures, including architectures with DSP and RISC-specific features as well as single instruction multiple data (SIMD) and very long instruction word (VLIW) processors.

Customers like Yokogawa are finding they can save significant development effort and achieve better quality of results by automating the application-specific instruction-set processor (ASIP) design process, said John Koeter, vice president of marketing for IP and systems at Synopsys. With Processor Designer, companies developing ASIP or fixed processing hardware in-house gain broad architectural flexibility to deal with evolving requirements without compromising performance, power or area.