Tensilica Introduces Third Generation ConnX 545CK

The ConnX 545CK is ideal for SOC dataplane signal processing because it allows system control and high-speed signal processing throughput in a single core with a single compiler and single instruction stream. It combines a base CPU controller with a DSP that can sustain eight simultaneous MAC operations on independent data pairs per cycle, utilizing the 160-bit vector registers.

The seamless blending of traditional CPU and traditional DSP characteristics makes all of Tensilica's ConnX brand DPUs uniquely well suited to a variety of wired and wireless communications applications, stated Steve Roddy, Tensilica's vice president of marketing and business development. The ConnX 545CK is a ready-to-use, off-the-shelf octal- MAC solution. And for designers seeking to tailor a DSP further, the ConnX 545CK can be augmented to perfectly suit a particular target application by utilizing the unique customization capabilities of Tensilica's Xtensa LX3 processor.

The ConnX 545CK features a3-issue VLIW architecture with eight 16-bit multipliers that operate in SIMD (single instruction, multiple data) mode. The core can sustain eight parallel multiply-accumulate operations per cycle. The compiler automatically vectorizes code to take maximum advantage of the architecture. It also has two 128-bit load/store units and a built-in Viterbi convolutional coder accelerator.

One of the unique features of the ConnX 545CK is the 32-bit input/output Queue interfaces that function like FIFOs (first in, first out), to bypass the system bus and communicate directly to streaming data interfaces. This allows much faster data throughput than traditional DSPs, which require memory-based load and store operations on each data element.