Home > News & Analysis > Tensilica Configurable Processors Used in Stanford Smart Memories Project

Analysis

Tensilica Configurable Processors Used in Stanford Smart Memories Project

28th February 2008

Tensilica

ES Admin

0 0

Tensilica Inc. has announced that Stanford University's Smart Memories Project used Tensilica's Xtensa LX2 configurable processor to develop a multiprocessor computing infrastructure for next generation applications. The Stanford Smart Memories Project has developed a prototype system-on-chip (SOC) design that provides the user the ability to program both the processor and the memory system of a chip-level multiprocessor. Using Tensilica allowed the Smart Memory team to focus on creating a flexible memory system that supports many different memory models, including message passing, coherent shared memory and transactional memory. The design is currently being evaluated for possible commercial deployment by a couple of large semiconductor companies.

It's exciting to see our processor cores enabling ground-breaking research on next-generation computing architectures, said Chris Rowen, Tensilica's president and CEO. Universities play a key role in driving major electronics innovations, especially in the grand-challenge problems in scalable multiprocessor architectures and software paradigms.

The Stanford team configured Xtensa as 3-way issue VLIW processors with seven stage pipeline, 64 general purpose registers, a 32-bit floating point using the TIE (Tensilica Instruction Extension) Language. The Smart Memories group has defined new interfaces to the memory, which allows the processor to respond to the meta-data bits in the memory so it can support various kinds of cache coherence. The resulting system is a hierarchical multiprocessor. Two Tensilica processors are placed in a tile, along with a number of programmable memory mats. Four tiles are then grouped with a programmable local memory controller to form a quad, and quads interconnect with each other and memory controllers through an on-chip network to form a Smart Memory chip.

Stanford researchers designed Smart Memories to efficiently support different programming models, allowing an application to be programmed and run in the model that gives the best performance and/or programming ease. Smart Memories can reconfigure its memory system to provide the unique memory access requirements for each of three major models.