Synopsys Announces Immediate Availability of Reprogrammable Non-Volatile Memory IP in 180-nm CMOS Process Technology

Synopsys' broad portfolio of MTP and FTP NVM IP solutions delivers optimized electrical performance for a wide range of end applications, including: performance trim and calibration in precision analog designs, data storage in ultra-low power wireless applications, or high endurance in real-time datalogging applications. These solutions help designers reduce the cost and risk of integrating NVM IP into their SoC designs.



A key advantage of the DesignWare AEON embedded NVM IP is that no high voltage generation circuitry is required – all programming and re-programming is done using a standard CMOS technology with no additional masks or process adaption. This allows designs to operate from a single core supply, eliminating the complication of generating a separate, high-voltage signal for NVM programming, or supporting a high-voltage I/O pad. In addition, DesignWare AEON NVM IP provides support for extended temperature ranges beyond industry standard (up to 125 degrees C for commercial and industrial products and up to 150 degrees C for automotive products), which enables designers to develop robust SoCs that can withstand harsh process, voltage and temperature variations. The DesignWare AEON products allow designers to choose the best configuration to optimize power, performance and area for their applications' SoCs:



• AEON/FTP Trim: ideal for analog and mixed-signal SoC designs, this solution provides area efficiency (256 bits in < 0.07 mm2) and offers up to 100 write cycles and additional flexibility over one-time programmable (OTP) solutions

• AEON/MTP RFID: targeting RFID and wireless SoC designs, this ultra-low power solution offers up to 1,000 write cycles, with read operation down to 1.0 V

• AEON/MTP EEPROM: fully qualified to automotive grade standards (AEC-Q100), this product provides support for up to one million write cycles at high temperatures (up to 150 degrees C)



Verayo's patented silicon 'DNA' technology – Physical Unclonable Functions (PUF) technology – provides an unclonable physical layer of security for our cost-effective RFID IC authentication solutions that target a broad range of mobile and near-field communication applications. For these RFID ICs, it is important for Verayo to leverage silicon-proven third-party IP that enable us to meet our strict cost and feature requirements, said Eric Duprat, CEO at Verayo. Implementing Synopsys' DesignWare AEON NVM IP in our latest mixed-signal RFID IC provided our solution with value-add features such as customer programmability and improved the performance and area of the design, while reducing integration risk and helping us achieve our time-to-market window.



Wireless and RFID companies are targeting the 180-nm process as the low-cost, high-performance node to deliver differentiated features and functionality in next-generation consumer electronics and automotive chip designs, said John Koeter, vice president of marketing for IP and Systems at Synopsys. With reprogrammable NVM IP technology that has shipped in more than three billion chips and is now fully qualified for 180-nm process nodes, Synopsys offers SoC designers a proven solution optimized for power, area and performance that lowers their integration risk and speeds their time-to-market.



Availability

The DesignWare AEON embedded NVM IP for 180-nm process technology is available now for several leading foundries. DesignWare AEON embedded NVM IP is also available for leading 65-nm to 250-nm process technologies.