Partnership to explore next-gen 5nm device & process technologies

This latest agreement between imec and Synopsys follows successfully completed collaborations on FinFET and 3D-IC technologies for the 10nm and 7nm technology nodes.

Working closely together, the joint Synopsys-imec team is investigating, among other topics, a vertical nanowire-nanosheet hybrid SRAM cell to target 5nm technology. Early studies show the benefits of nanowire-nanosheet technology in density and performance compared to conventional FinFETs and lateral nanowires. Synopsys' Sentaurus TCAD tools that support this collaboration are used by technology development teams at foundries and Integrated Device Manufacturers (IDMs) for device architecture selection, design and process optimisation.

Using early versions of Synopsys' TCAD models allows the imec project team to explore a range of topics including fundamental device physics (material science, quantum transport and strain engineering), Middle-of-Line (MoL) local interconnects and the optimisation of parasitics. A significant part of the analysis involves 3D process and electrical simulations to identify device and interconnect reliability solutions for highly scaled circuits.

The Synopsys TCAD tools used in this collaboration include the industry-standard simulators Sentaurus Process, Sentaurus Device, Sentaurus Interconnect and Raphael. 3D process structures are read into Raphael for extracting the resistance and capacitance of MoL structures and are combined with Sentaurus-derived compact models for circuit simulation with Synopsys' HSPICE tool. This simulation flow enables technologists to evaluate the speed and power consumption of ring oscillators and other test circuits in the early stage of technology development, thereby closely linking technology development and selection with circuit-level targets.

"At imec, we focus on bringing the semiconductor industry leaders together to deliver future technologies," said An Steegen, Senior Vice President, Process Technologies, imec. "We are excited to expand our co-operation with Synopsys, the primary TCAD provider, to explore next-gen device and process technologies for 5nm. This continued tight collaboration with Synopsys will enable us to tackle the physics and engineering of advanced devices and introduce a device design infrastructure for the industry."

"This is the first time a process-calibrated TCAD simulation flow has been used to comprehensively study the process, device and circuit architectures so early in the technology path-finding process," added Anda Mocuta, Logic Device Manager, imec.

"This expanded collaboration with imec builds on the success of previous collaborations to address key challenges at the 5nm technology node," commented Howard Ko, Senior Vice President and General Manager, Silicon Engineering Group, Synopsys. "Imec's advanced technology prototyping and characterisation capabilities make it a suitable partner for our development and calibration of advanced Sentaurus TCAD models to address the significant technical and business challenges that our customers face in the development of 5nm node technologies."