Aldec Launches Free Online UVM Training

As a global industry leader, Aldec is committed to offering educational opportunities and resources to help busy engineers get up to speed quickly.

“Engineers from locations around the world, now have access to world-class technical training – at no cost,” said Jerry Kaczynski, Aldec Research Engineer and contributor to the Fast Track™ training curriculum. “These private, online trainings will allow the user to go through each module at their own pace, and even go back to review material. Each individual module also offers a quick self-test to ensure the module is grasped before proceeding.”

The premiere training course for the new program is ‘Fast Track to UVM ONLINE’, taken directly from Aldec’s most popular onsite training curriculum:

Fast Track to UVM ONLINE

This course introduces hardware designers familiar with Design Subset of SystemVerilog into the brave, new world of Universal Verification Methodology (UVM).

Typical hardware designers may not be responsible for maintaining the complete verification suite of large system-level designs, however they often work with verification engineers while creating these environments. For this reason, ‘Fast Track to UVM’ begins with an introduction, or refresher, of SystemVerilog constructs used in UVM (classes, objects, randomization, coverage, interfaces), provides outline of TLM, discusses general structure of UVM and progresses to more a detailed description of verification components and their usage.