eSilicon Selects Synopsys' Custom IC Design Solution and Tapes Out 28-nm Designs

Custom memory IP developed by eSilicon uses complex, state-of-the-art memory architectures—including cache, content-addressable memory (CAM), SRAM, ROM, and multi-port register file (MPRF) IP—that must be created using a custom design flow to meet increasing performance and density constraints.

eSilicon successfully adopted the complete Synopsys custom solution, including the Galaxy Custom Designer schematic and layout editor, HSPICE and CustomSim circuit simulators, IC Validator design rule checking and layout versus schematic (DRC/LVS) solution, StarRC extraction tool, and PrimeYield foundry-qualified manufacturing compliance tool for final physical signoff.

To support our custom memory IP business, we needed a complete, integrated custom IC design tool suite that could be rapidly adopted and deployed, said Patrick Soheili, vice president of marketing and business development and general manager of IP solutions at eSilicon. The unified custom IC design solution from Synopsys, including Custom Designer, provides the productivity and performance our engineers need to quickly design and tape out IP at the 28-nanometer node.

Custom Designer continues to gain adoption because of the breadth and depth of Synopsys' overall custom solution, said Bijan Kiani, vice president of product marketing at Synopsys. The availability of iPDKs at advanced process nodes, combined with the productivity of our unified custom solution, allows designers to choose Synopsys' custom implementation solution to achieve higher productivity in an open, standards-based environment.