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EdXact ‘s Parasitics Analysis and Netlist Reduction Technology Endorsed in a Testimonial on Layout Optimization of Power-MOS Devices at DATE 2011

10th March 2011

Edxact

ES Admin

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EdXact, post-layout verification specialist will be endorsed by ST-Ericsson in a testimonial on Optimization of Power-MOS Structures dedicated to Energy Management ICs at the upcoming DATE 2011 conference being held at AlpExpo in Grenoble, France.

Edxact will also showcase the latest features of Jivaro and Comanche, its netlist reduction and parasitics analysis platforms, in booth 23 from 15 to 17 March at the DATE 2011 conference.

Title : « Optimization of Power-MOS Structures dedicated to Energy Management ICs»

Abstract:

Impact of metal routing on 'rdson' parameter of power-MOS devices is increasing with more advanced process nodes (65nm, 40nm). Capacity of Comanche tool to quickly extract thousands of pin to pin resistances enables us to achieve layout optimization by analysing resistances distribution from pads to any individual transistor. In addition, Jivaro reduction makes possible the spice simulation of the structure including both parasitic resistors and functional devices to extract rdson parameter.

Speaker : Jérôme Lescot, ST-Ericsson

When/ Where

Tuesday, March 15, 2011 - 17:50 - 18:10pm,

Exhibition Theatre, DATE Exhibition Floor