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Edxact

Edxact Articles

Displaying 1 - 8 of 8
Analysis
13th March 2013
EdXact Participates at CDNLive Silicon Valley on March 12

EdXact is going to exhibit as a technical partner at the Designer Expo at CDNLive Silicon Valley next week. EdXact will showcase its product families that have been build on a common analysis platform Alps.

Analysis
10th March 2011
EdXact ‘s Parasitics Analysis and Netlist Reduction Technology Endorsed in a Testimonial on Layout Optimization of Power-MOS Devices at DATE 2011

EdXact, post-layout verification specialist will be endorsed by ST-Ericsson in a testimonial on Optimization of Power-MOS Structures dedicated to Energy Management ICs at the upcoming DATE 2011 conference being held at AlpExpo in Grenoble, France.

Design
2nd February 2011
EdXact grows business by more than 60%, reports sixth consecutive profitable quarter

EdXact SA, physical layout verification specialist best known for netlist reduction software Jivaro, announced a successful 2010 for its business and the completion of the sixth consecutive quarter of profitability.

Analysis
14th June 2010
TSMC Selected EdXact Jivaro for 28nm Analog and Mixed-Signal Reference Flow

EdXact, post-layout verification specialist today announced that its netlist reduction software Jivaro™ has been included in TSMC’s Analog/Mixed-Signal (AMS) Reference Flow for 28nm analog and mixed-signal circuit design. Analog, mixed-signal, and RF design teams at leading semiconductor companies worldwide now can use Jivaro to efficiently reduce post layout netlist parasitics to speed up their overall simulation time for their 28nm AMS proj...

Design
20th May 2010
EdXact to Enhance Interactive Debugging Capabilities, Hierarchical File Handling and Improved Selectivity Features to Its Post-Layout Analysis Tools at 47th DAC

EdXact, post-layout verification specialist will showcase the latest tool enhancements of its parasitics reduction and analysis tools. Among the highlights of the tool releases 5.0 of Jivaro™ and 3.2 of Comanche ™are hierarchical file handling, additional features to drive the selectivity options and integrations into different graphical user interfaces in order to facilitate interactive network debugging facilities.

Design
5th February 2010
MediaTek Deploys EdXact’s Jivaro Technology for Analog Circuits

Backend verification specialist EdXact SA and MediaTek Inc. a leading fabless semiconductor company for wireless communications and digital multimedia solutions today announced that they have entered a strategic relationship to deploy EdXact’s netlist reduction platform for analog circuits.

Design
15th July 2009
edXact Releases Electromigration-Aware Version of Jivaro and Production-Proven Version of Comanche. To Preview Jivaro 5.0 at DAC

edXact SA, layout verification specialist, today announced that it will release versions 4.3 of its flagship simulation acceleration software Jivaro and version 3.1 of its parasitic rule checking analyzer Comanche at DAC. edXact also will showcase the new path finder feature as a major upgrade of the upcoming Jivaro 5.0 generation of its netlist reduction tools. Jivaro 4.3, preview Jivaro 5.0 and Comanche 3.1 will be demonstrated in Booth # 3765 ...

Design
20th January 2009
edXact major contributor in CILOE cluster dedicated to HPC and SaaS

Backend verification specialist edXact SA today announced that it is a major contributor in the joined development and innovative business model project, dubbed CILOE, led by Minalogic to help SMEs to develop massively parallel and optimized versions of their software on threaded processors and computing farms.

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