EdXact Participates at CDNLive Silicon Valley on March 12

-Jivaro, EdXact's netlist reduction engine allows to reduce the overhead of interconnect parasitic components on circuit simulation time with a very high degree of accuracy and efficiency. Jivaro has several tight links at different places in the design environment of Cadence.

-Viso, EdXact's circuit analysis tool provides fast analysis capabilities to the designer. Quickly verifying the resistance between ports, determining the cross-coupling between nets, estimating the delay, fast calculation of RdsOn for large embedded PowerMOS devices, are the tasks Viso solves on a daily basis.

-Belledonne, EdXact's circuit comparison tool with emphasis onparasitics allows to compare quickly and accurately very large netlists in order to tune parameters of extraction tools, find differences between two versions of a design, increase robustness of design kits.

CDNLive Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.