Crocus Awarded IARPA Contract To Develop 8-bit Per Cell Memory

The company plans to demonstrate multi-bit per cell capability that will vastly exceed the current state-of-the-art limit of the number of bits that can be stored per memory cell. This will greatly reduce the energy consumed per written-bit compared to any other variety of memory technology, including DRAM, Flash, SRAM and MRAM.

In addition to the expected cost benefits of such a structure, the benefits for chip security and enhanced embedded crypto-processors are quite significant. In these applications, secret keys are stored in the embedded memory. Multiple bits per cell greatly complicate the ability for hackers to physically have access to the secret keys using known crypto analysis methods. Secure embedded crypto-processors are currently deployed in applications such as passports, banking cards and SIM telephone cards.

Traditional magnetic memories are based on memory cells where each cell stores a single bit of data. Crocus plans to demonstrate 8-bits per cell capability through the work to be performed under the IARPA contract by combining two innovative magnetic structures, the Axial Induced Moment and the Multi-Junction Magnetic Tunnel Junction. AIM uses a variable angle magnetic moment vector to encode binary data in a magnetic cell. Crocus proposes to demonstrate AIM with 16 storage angles yielding 4-bits per AIM cell. The MJM structure uses two tunnel barriers stacked in a single MLU cell. In a combined AIM/MJM structure, the two storage layers of MJM are operated with each layer supporting a rotating AIM storage vector. The combined AIM/MJM structure is capable of storing 16 states in each of two independent storage layers, resulting in 256 possible stored states or 8-bits per cell storage density.

“AIM and MJM are breakthrough magnetic structures within Crocus’ MLU architecture that enable the unprecedented storage capability of up to 8-bits per cell,” said Douglas Lee, vice president, system strategy and corporate product development at Crocus Technology. “The current semiconductor non-volatile memory state-of-the-art is 3-4 bits per cell, as achieved in NAND Flash memory and is reaching the physical limits of floating gate memory technology. The current state-of-the-art in MRAM is only 1 bit per cell storage.”

“Crocus’ multi-bit MLU architecture enables new and unique applications that are not addressable through any other silicon or magnetic memory technology,” said Bertrand F. Cambou, executive chairman of Crocus Technology. “These new applications are of particular value to security applications, particularly for their ability to provide unprecedented capabilities with regard to tamper resistance and authentication, higher memory density within existing lithographic manufacturing infrastructure and expanded operating temperature ranges up to 200 degrees Celcius.”

This work will be funded by IARPA, which invests in high-risk / high-payoff research programs that have the potential to provide the U.S. with an overwhelming intelligence advantage over future adversaries. This IARPA contract represents the first phase of the multi-bit cell development and is scheduled to be completed in one year.