DOCSIS protocol analyser chosen to test chipset

Developed with major industry players and designed for both DOCSIS 3.0 and DOCSIS 3.1, the DP-1000 provides users with state-of-the-art tools for analysing, debugging, maintaining and monitoring local networks and Internet connections.

Multiple system operators (MSOs), chipset manufacturers, product developers and certifications bodies use it to quickly find and correct trouble spots in order to maintain the highest quality of service possible.

Optimised for real-time signal processing with FPGA technology, the DP-1000 analyzes up to 32x8 single or bonded US/DS channels (DOCSIS 3.0) and 2x1 OFDM US/DS channels (DOCSIS 3.1), and includes numerous channel-filtering, demodulation, triggering, display, and upgrade features.

“Intel was seeking a solution to test its new chipset for D3.1 as well as D3.0, validate CableLabs specifications for the MAC-layer and parts of the PHY-layer, as well as evaluate CMTS interoperability,” said Alex Pelland, Director of Broadband Test Strategy at Averna. “Our DP-1000 DOCSIS Protocol Analyser was a perfect fit for these requirements. Since DOCSIS 3.1 will enable a new generation of sophisticated products and cable services, broadband product developers like Intel will benefit from the DP-1000’s ability to accelerate the important validation and certification phases.”

The analyser offers an input frequency range of 100 MHz–1.8 GHz DS, 5 MHz –200 MHz US and it has scquisition cards of 200 MHz bandwidth each. It is contained in a single, 19in (48 cm), 4U rack for minimal footprint (60 lbs/27 kg).

The FPGA-based architecture is highly flexible, configurable, upgradable and extendable.