Collaboration to accelerate 3D flash memory verification

Compared to traditional Flash devices, 3D Flash devices have much larger memory arrays, more complex analogue and programming circuits, and extensive power distribution network. Additionally, due to the stacked memory array structure, 3D Flash designs must deal with increased coupling effects due to layout parasitic elements. This increased complexity results in multi-day simulation times when using existing circuit simulation technology. Through close collaboration with Toshiba Memory, the latest release of FineSim Pro FastSPICE delivers several key technologies specifically optimised for 3D Flash simulation, for efficient handling of massive array structures, large power distribution network, increased layout parasitic elements, and high-precision analogue circuits.

"FineSim has been our signoff circuit simulator since early 2000. Our long collaboration with Synopsys has enabled us to develop best-in-class Flash memory products for a broad range of applications," said Shigeo (Jeff) Ohshima, Technology Executive SSD Application Engineering of Toshiba Memory Corporation. "By working closely with Synopsys we're able to deploy FineSim Pro for verification of our latest BiCS Flash memories and meet our stringent quality and reliability requirements."

Paul Lo, Corporate Vice President of Engineering in the Design Group at Synopsys stated: "Advanced flash memory designs require extensive circuit simulation to ensure design robustness, reliability, and cost competitiveness. Our team is committed to continuing our close collaboration with Toshiba Memory Corporation to deliver novel circuit simulation technologies to meet the challenging needs of simulating complex 3D NAND Flash memories and enable Super Chips with Synopsys."