eASIC and Radiocomp Deliver Low Power 6G CPRI v4.1 REC Solution

CPRI is the most widely deployed interface between baseband and radio sections of a wireless base station and has traditionally been implemented using expensive and high power consumption FPGAs. The availability of the eASIC CPRI REC solution allows FPGA designers to engage in cost and power reduction efforts much sooner, and at a fraction of the development cost for cell-based ASICs.

“We are delighted that eASIC has selected our CPRI v4.1 REC IP technology to expand its wireless portfolio. Our implementation of the core onto Nextreme-2T shows exceptionally high signal integrity when compared to some FPGA-based solutions. We believe that this will enable base station vendors to quickly design Nextreme-2T-based CPRI REC solutions at a lower system cost and with reduced power consumption, much faster than before,” said Christian Lanzani, Senior Product Manager in Radiocomp ApS.

“We are seeing very little innovation from FPGA vendors to help customers reduce cost and power in base station designs,” commented Jasbinder Bhoot, eASIC Vice President Worldwide Marketing. “The inclusion of the CPRI REC IP to our silicon proven serdes capability means that at last radio base station designers can have a lower cost and lower power alternative to FPGAs. In addition, the signal integrity of the eASIC solution also demonstrates that eASIC’s Nextreme-2T transceiver is fully compliant with all CPRI V4.1 specifications.” added Bhoot.

The Radiocomp CPRI v4.1 core has already been verified in both FPGAs and eASIC devices and features:

* Built-in support for CPRI v4.1 REC and backwards compatible mapping methods
* Programmable Line rates up to 6.144 Gbps.
* Up to 32 antenna carriers per IP core
* Integrated HDLC and 10/100 Ethernet MAC controllers or external MII interface
* Portable HDL code for easy migration from FPGAs to eASIC