Siemens collaborates with TSMC on design tool certifications

The Siemens EDA offerings has certified for TSMC’s N3 and N4 processes include the Calibre nmPlatform, Siemens’ industry-leading physical verification solution for IC sign-off, as well as the Analog FastSPICE Platform, which provides leading-edge circuit verification for nanometer analog, radio frequency (RF), mixed-signal, memory, and custom digital circuits, claims the company. Siemens and TSMC have also been working closely on advanced process certifications for Siemens’ Aprisa place-and-route solution, to help assist joint customers achieve smooth and rapid silicon successes with Aprisa at the foundry’s most advanced processes.

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, executive vice president, IC-EDA for Siemens Digital Industries Software.  “Siemens is proud to collaborate with TSMC to continue to deliver difference-making technologies that enable our mutual customers to deliver IC innovations to market more quickly.”

Siemens’ commitment to supporting the latest TSMC processes also extends to the TSMC 3DFabric technology. The company has successfully completed the design requirements for TSMC’s cutting-edge 3DFabric design flows. As part of the qualification process, Siemens enhanced its Xpedition Package Designer (xPD) tool to support Integrated Fan-Out Wafer Level Packaging (InFO) design-rule handling with automated avoidance and correction. Calibre 3DSTACK, DRC and LVS are furthermore enabled and certified for the latest TSMC 3DFabric technologies, including InFO, CoWoS, and TSMC-SoIC. For customers, these 3DFabric enablement milestones translate to shorter design and signoff cycles with fewer errors associated with manual interventions. 

Siemens has partnered with TSMC to build a Design for Testability (DFT) flow for TSMC’s 3D silicon stacking architecture. Siemens’ Tessent software provides a leading-edge DFT solution based on hierarchical DFT, SSN (Streaming Scan Network), enhanced TAPs (test access ports) and IEEE 1687 IJTAG (internal joint test action group) network technologies, all of which are IEEE 1838 compliant. Designed for scalability, flexibility and ease-of-use, the Tessent solution helps customers optimize resources associated with IC test technology.

“Siemens continues to increase its value to the TSMC OIP ecosystem by offering more features and solutions in support of our most advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “We look forward to our continued collaboration with Siemens to help our mutual customers accelerate silicon innovations with design solutions combining Siemens’ leading-edge electronic design automation (EDA) technologies with TSMC’s latest process and 3DFabric technologies.”

Finally, Siemens’ close collaboration with TSMC recently enabled the Calibre tools to demonstrate dramatic performance and scaling improvements for one of the world’s foremost IC design firms within a leading cloud computing environment. Made possible by the optimisation of the latest setup, decks and engine technologies for cloud environments within Calibre, these advancements can help joint customers realize faster time-to-tapeout and time-to-market. To learn more, please make plans to view Siemens’ technical presentation during the TSMC 2021 Online OIP Ecosystem Forum.