Silicon test under scrutiny at Synopsys event

13th October 2014

Synopsys Inc

Mick Elliott

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Synopsys will host its annual Test Special Interest Group (SIG) event during the International Test Conference (ITC) 2014 in Seattle (Oct 21-23). Delegates will hear a plenary keynote speech from Synopsys Chairman and co-CEO Dr. Aart de Geus, and be able to attend numerous technology sessions featuring Synopsys test experts throughout the three-day conference.

The SIG event is scheduled for October 20.

Test experts from leading semiconductor companies and foundries will discuss the latest in silicon test technologies and share their experiences and insights on how to achieve higher test quality and lower test cost, faster. Topics to be discussed include: new fault models for emerging process nodes and FinFETs, new compression technologies, latest diagnostic techniques and advanced memory test and repair.

The Synopsys synthesis-based test solution is comprised of DFTMAX Ultra, DFTMAX and TetraMAX for power-aware logic test and physical diagnostics; the DesignWare STAR Hierarchical System for hierarchical test of IP and cores on an SoC; the DesignWare STAR Memory System for embedded test, repair and diagnostics; Yield Explorer tool for design-centric yield analysis; and the Camelot software system for CAD navigation.

Synopsys' test solution combines Design Compiler RTL synthesis with embedded test technology to optimise timing, power, area and congestion for test as well as functional logic, leading to faster time-to-results due to zero or minimal design iterations. The solution contains value links among the test products and across the Synopsys Galaxy Design Platform to enable faster turnaround time meeting both design and test goals, higher defect coverage and faster yield ramp.