imec to demonstrate building blocks at 2024 IEEE meeting

The devices outperform state-of-the-art superconducting technology and meet the target specifications for superconducting digital systems designed to revolutionise the roadmaps for AI and HPC.

Being scalable and compatible with CMOS fabrication technology, the demonstrated technology bridges the gap from lab-scale feasibility studies to industrial fabrication. Compute systems based on superconducting digital technology promise to significantly outperform state-of-the-art CMOS-based processors by taking advantage of the zero electrical resistance of the superconducting materials at cryogenic temperatures.

Imec, through a system-technology co-optimisation study, demonstrated that first-generation superconducting digital systems deliver 100x more system power efficiency and 10-100x better performance than a 7nm-CMOS-based system. To meet these target system specifications, a scalable technology is needed to fabricate the key building blocks of such superconducting digital circuits: superconducting interconnects (wires and vias), Josephson junctions serving as the active elements, and tunable MIM capacitors for power delivery.

At 2024 IEDM, imec will demonstrate functional NbTiN-based interconnects, Josephson junctions, and MIM capacitors fully compatible with CMOS processing and temperatures, with key metrics exceeding best-published results.

For the superconducting interconnects, a semi-damascene integration process was used to build a two-metal-level scheme with wires and vias having critical dimensions down to 50 nm. Measurements at cryogenic temperatures reveal a critical temperature larger than 13K and a critical current density J_c>120 mA/µm² – a world record at such a small scale.

The Josephson junctions, with amorphous Si (aSi) sandwiched between two superconducting NbTiN layers, exhibit record-high J_c>2.5 mA/µm². Imec researchers also demonstrated tunable HZO-based capacitors with NbTiN electrodes, having a high capacitance density of ~28 fF/µm². With these characteristics, all three modules meet the process specifications in the envisioned system design.

“Key to the outstanding results is the adoption of novel integration schemes in combination with NbTiN, a superconducting material with much better scaling potential than Nb," said Anna Herr, scientific director at imec USA Florida. "The technology is scalable to high device densities, already exceeding superconducting state-of-the-art with 500x. Imec’s semi-damascene integration scheme is expandable to multiple metal levels. It lays the foundation for building a 16-metal-level interconnect fabric in which the junctions and capacitors must be embedded to benefit from the zero-wire resistance. The proposed technology can also withstand conventional BEOL processing temperatures (420°C) and is compatible with standard 300mm CMOS processing. We believe that our demonstration is a crucial step towards industrial processing in commercial foundries.”