Top EDA Companies Endorse Tensilica's Pin-Level SystemC Models

The pin-level models are a natural extension of Tensilica's pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC), and allow designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators, and do not require the usage of any specialized hardware/software co-simulation tool.

IC designers now can use Tensilica's fast, instruction-accurate functional models for early design exploration and software development, more detailed pipeline accurate models with TLM interfaces connected to other devices modeled in SystemC, or cycle-accurate pin-level SystemC models to verify the interconnection of the processor with tightly coupled hardware blocks via Verilog simulation. The models can be run inside all of the leading RTL simulator tools including Incisive Enterprise Simulator from Cadence, Questa from Mentor Graphics, and the VCS functional verification solution from Synopsys.


The market requires a functional verification solution that supports SystemC TLM and accurate RTL hardware/software co-verification stated Steven Brown, director of marketing, system design and verification, Cadence. The Tensilica TLM and pin-level XTSC models, along with Incisive, provide the speed and accuracy needed for applying the Open Verification Methodology (OVM) to both TLM and RTL design verification.
Mentor Graphics has seen the number of users performing hardware/software co-simulation grow, said Stephen Bailey, Director of Verification Solutions, Mentor Graphics. By providing Transaction-level and Pin-level SystemC modeling interfaces, Questa users will be able to verify designs incorporating Tensilica cores throughout the entire design flow.

Synopsys and Tensilica have worked together for more than 10 years to address the tough verification challenges for mutual customers, said Swami Venkat, senior director marketing, Verification Group at Synopsys, Inc. VCS and Innovator have been supporting verification at multiple levels of abstraction, including transaction-level SystemC models, and the support for Pin-level XTSC models in VCS is a natural evolution of this collaboration.

Our DPUs are often found tightly coupled to user logic deeply embedded in the SOC dataplane, and our goal is to continue to provide tools and models that improve designer productivity, stated Chris Jones, Tensilica's director of strategic alliances. Pin-level SystemC modeling provides a solution to customers who want to exercise the connections between the processor and the external logic with real software running on the target. And we deliver this functionality without burdening the customer with the purchase of new co-simulation tools.