Verification platform selected for RISC-V processor designs

Synopsys claims that its leadership position in these critical verification technology areas, combined with native integrations among these products, has enabled SiFive to meet aggressive goals for scalable verification of customised RISC-V processors and SoCs targeted for IoT, edge computing, machine learning, storage and other applications.

"SiFive was founded by the creators of the free and open RISC-V architecture with an innovative approach that brings the power of open source, agile hardware design and verification to the semiconductor industry," said Renxin Xia, Vice President of engineering at SiFive. "In Synopsys, we found an innovative partner with leading verification technologies that provide our team with the productivity and flexibility required to deliver our customised processor IP and silicon solutions."

With the exponential growth of verification complexity, achieving verification closure requires a broad set of technologies including advanced simulation, verification IP, advanced debug, static and formal verification, low-power verification and coverage closure. To address this substantial complexity, Synopsys continues to have the largest R&D investment in verification spanning the entire verification flow. This includes VCS simulation, VC verification IP, Verdi advanced debug, SpyGlass RTL signoff solutions as well as next-gen VC Formal verification solutions. The native integration of these solutions further enables design teams to achieve faster performance, lower power and higher productivity for accelerated verification closure.

"Synopsys is addressing the need for faster time-to-market with our leading portfolio of verification software technologies," said Ajay Singh, Senior Vice President of R&D in the Synopsys Verification Group. "Our collaboration with SiFive demonstrates the performance benefits of our Verification Continuum platform required for their RISC-V processors and custom SoCs."