UMC and Cadence collaborate on 3D-IC hybrid bonding reference flow

UMC’s hybrid bonding solutions are now ready to support the integration across a broad range of technology nodes that are suitable for Edge AI, image processing, and wireless communication applications. Using UMC’s 40nm low power (40LP) process as a wafer-on-wafer stacking demonstration, the two companies collaborated to validate key 3D-IC features in this design flow, including system planning and intelligent bump creation with Cadence’s Integrity 3D-IC platform, the industry’s first comprehensive solution that integrates system planning, chip and packaging implementation, and system analysis in a single platform.

“Interest in 3D-IC solutions has increased notably in the past year as our customers seek ways to boost design performance without sacrificing area or cost,” said Osbert Cheng, Vice President of Device Technology Development & Design Support at UMC. “Cost-effectiveness and design reliability are the pillars of UMC’s hybrid bonding technologies, and this collaboration with Cadence provides mutual customers with both, helping them reap the benefits of 3D structures while also accelerating the time needed to complete their integrated designs.”

"With increasing design complexity for IoT, AI, and 5G applications, wafer-on-wafer technology automation is increasingly important for chip designers,” said Don Chan, Vice President, R&D in the Digital & Signoff Group at Cadence. “The Cadence 3D-IC flow with the Integrity 3D-IC platform is optimised for use on UMC’s hybrid bonding technologies, providing customers with a comprehensive design, verification, and implementation solution that enables them to create and verify innovative 3D-IC designs with confidence while accelerating time to market.”

The reference flow, featuring Cadence’s Integrity 3D-IC Platform, is built around a high-capacity, multi-technology hierarchical database. The platform offers design planning, implementation, and analysis of full 3D designs within a single, unified cockpit. Multiple chiplets in a 3D stack can be designed and analysed together through integrated early analysis for thermal, power and static timing analysis. The reference flow also enables system-level layout versus schematic (LVS) checking for connectivity accuracy, electric rule-checking (ERC) for coverage and alignment checking, and thermal analysis for heat distribution in a 3D stacked-die design structure.

In addition to the Integrity 3D-IC platform, the Cadence 3D-IC flow also includes the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Pegasus Verification System, Voltus IC Power Integrity Solution, and Celsius Thermal Solver for system analysis.