TSMC certifies Synopsys design tools for 10nm FinFET technology

The certification includes routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE, and interoperable process design kits for FinFET processes. Built on a history of collaboration between TSMC and Synopsys, this certification ensures SoC designers can get optimum power, performance and area from the 10nm process.

"Synopsys is ready with complete, certified, digital and custom implementation tools, as designers move to the 10nm process," said Bijan Kiani, Vice President of Product Marketing, Synopsys' Design Group. "This collaboration with TSMC for 10nm ensures that the proven platform can be deployed for predictable design closure."

"Our deep and extensive collaboration with Synopsys on critical design-enablement technologies has continued beyond the 16nm FinFET Plus process," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "Synopsys and TSMC are addressing our customers' needs to deliver highly optimised design solutions for our most advanced 10nm FinFET process."

Key Synopsys tools certified by TSMC include:

• IC Compiler II: Certified by TSMC for V0.9 version of the 10nm process with immediate availability of technology files and implementation collateral.
• IC Validator: Fully color-aware signoff physical verification for FinFET designs.
• StarRC extraction solution: Support for 10nm multi-patterning, full color-aware variation modeling and 3D FinFET modeling to enable industry-leading signoff accuracy.
• PrimeTime timing signoff solution: Support for 10nm low voltage with advanced waveform propagation, Liberty Variation Format-based process variation and advanced placement rule engineering change order guidance to accelerate timing closure and leakage recovery.
• PrimeRail: Accurate gate-level static and dynamic IR-drop analysis, colour-aware and power/ground electro-migration rules support.
• NanoTime: SPICE-accurate transistor-level static timing analysis of 10-nm embedded SRAMs.
• Galaxy Custom Designer schematic editor and Laker Layout Editor: Support for full coloring flow; track-pattern support, in-design EM/IR calculation and integration with CustomSim EM/IR analysis for debugging signoff errors in the layout.
• HSPICE, CustomSim and FineSim simulation products: Support for 10-nm FinFET device modeling with self-heating effect and delivery of accurate circuit simulation results for analog, logic, high-frequency and SRAM designs.
• CustomSim also supports 10nm EM rules for accurate transistor-level EM and IR-drop analysis.