Toshiba shortens design cycle with Synopsys place and route solution

Driven by the very attractive runtime speed-ups, Toshiba began using IC Compiler II soon after market introduction and has since expanded its usage across groups. Toshiba is a leader in IC design, fielding a variety of solutions in NAND/SSD, microcomputers, wireless communications equipment ICs, automotive devices, ASSPs, logic ICs and ASICs. The vast majority of the company's designs are performance-critical in nature, requiring Toshiba to employ the very best in design technology. The decision to expand usage of IC Compiler II to implement performance-critical designs stands to help Toshiba meet their aggressive market windows and Quality-of-Results (QoR) objectives.

Kazunari Horikawa, Senior Manager, Design Technology Development Department, Mixed Signal IC Division, Storage & Electronic Devices Solutions Company, Toshiba, commented: "Our external and internal customers always have very aggressive requirements for power, performance, area and very short design cycle, making it imperative that we have the best design technology available. Having already taped-out over a dozen designs with IC Compiler II, we have come to rely on it as our primary solution. We have been impressed with its very fast TAT while providing superior QoR. With expanded usage of IC Compiler II, which will be continually improved by Synopsys, we are confident that our design teams are well equipped to offer the highest QoR possible across our technology portfolio."

IC Compiler II is a state-of-the-art place and route system designed from the ground up to deliver the highest productivity and best QoR for designs across process nodes. Architected around a modern, low memory footprint and natively multi-threaded infrastructure, IC Compiler II is able to handle designs with more than 500 million placaeble instances hierarchically and has proven capacity for more than 10-million-instance block implementations. With its optimised place and route focused data model, coupled with an extensible library system that offers unique, geographically separated development capabilities, IC Compiler II eases user adoption by supporting industry-standard input and output formats, as well as familiar interfaces and process technology files.

IC Compiler II delivers industry-leading, ultra-high-capacity automated design planning, unique clock-building technology and patented global-analytical optimisation that results in a convergent design implementation flow. Together, these technologies enable enhanced QoR across power, performance and area implementation metrics as well as accelerated time-to-market. The culmination of numerous years of engineering innovation, these industry-first technologies enable IC Compiler II to deliver five times faster runtime within half the memory footprint while concurrently requiring half the iterations required to achieve the same target QoR. This ultimately results in a step-change boost in throughput and designer productivity.

"We share a long history of success with Toshiba, and they have been a key lead partner through the development and deployment of IC Compiler II. Gaining plan-of-record status for IC Compiler II for Toshiba's performance-critical designs underscores the many game-changing, QoR-focused technologies that are at the very core of this exciting product," added Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys.