Timing closure & signoff reduces required ECO iterations

Companies that have deployed PrimeTime ADV include Achronix Semiconductor, All Winner Technology, GUC, Infineon, Renesas, Samsung, ST and Toshiba. Timing closure is one of the biggest challenges highlighted by chip designers, often encompassing 30% of the physical implementation design schedule.

Traditional ECO solutions are no longer scaling to the complexity of timing closure and the pressure to improve performance and reduce power and area at emerging and established technology nodes. Further, highly dense designs in terms of routing and cell placement resources make development of ECO solutions costly. Hence, designers are looking to move away from traditional ECO solutions to more intelligent solutions to speed up the ECO schedule.

To address this challenge, PrimeTime ADV provides a physically aware timing and power recovery solution built on the PrimeTime signoff timing engine. This enables signoff quality timing which comprehends global timing effects like splitting parasitics, crosstalk impact and On-Chip-Variation (OCV), something existing commercial add-on ECO solutions lack.

Signoff correlation, essential for faster timing closure, is deficient in non-signoff timing tools, a situation which leads to costly ECO iterations. PrimeTime ADV's signoff-driven ECO guidance, when tightly integrated with Synopsys' leading StarRC extraction solution and IC Compiler physical implementation solution, delivers the best single-pass results using techniques such as on-route-buffering. With the recent PrimeTime ADV release, leakage recovery has been extended to total power recovery, assisting the mobile and consumer designs to further reduce their total power.

“Achronix is focused on achieving maximum clock speeds for our next-gen 14nm FPGAs. Having the best development tools is critical for us to increase our competitive advantage beyond our current 22nm Speedster22i FPGA products,” said Chris Pelosi, Director of Engineering, Achronix. “With Synopsys' PrimeTime ADV tool as part of our development kit, our designers can achieve our high frequency targets and cut the design cycle time.”

“Delivering automated solutions that enable our customers to achieve time-critical and aggressive timing and power goals with confidence is a major focus at Synopsys,” said Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys. “PrimeTime ADV's plug-n-play ECO solution, tightly coupled with StarRC and IC Compiler, helped our customers quickly adopt and deploy this technology in their timing closure flow.”