Tensilica Announces Availability of Atlas Reference Architecture Dataplane Processors for a Complete Baseband PHY for LTE, HSPA+ and WiMAX

Our LTE and HSPA+ products have propelled us as the leader for LTE baseband IP cores, stated Eric Dewannain, Tensilica's vice president and general manager of the Baseband Business Unit. By completing our offering with these additional dataplane processors, we can help other LTE and HSPA+ chipset suppliers achieve a faster time-to-market, while also achieving very low power and minimal size.

The ability to develop these optimized dataplane processors in a short time frame is a testimonial to the power of our patented DPU core foundation and tools which enables us to quickly create and optimize IP cores, he added.

The ConnX BBE16, introduced February 2010 (see press release dated February 8, 2010), is the single DSP part of the Atlas reference architecture, as it is built around a core vector pipeline made of sixteen 18bx18b MACs (multiply accumulators). ConnX BBE16 is optimized for performance of DSP kernel operations such as FFT (fast Fourier transform) and FIR (Finite Impulse Response) as well as matrix multiplies. This DSP core is optimized to give strong performance per power and area.
There are several other functions that must be implemented for a fully functional PHY system, and these are better implemented in function-specific DPUs to offer lower power and smaller size and address the control functions required. The three other Atlas components are:

- The ConnX Soft Stream Processor (ConnX SSP16), a 16-way SIMD (single instruction, multiple data) baseband core optimized for the processing of soft bits, used for the acceleration of wireless communication PHY routines such as Viterbi, HARQ, and de-rate matching, as well as data manipulation and movement operations.

- The ConnX Bit Stream Processor (ConnX BSP3), a baseband core optimized for the processing and control of bit streams, used for the acceleration of wireless communication PHY routines such as bit mapping, bit interleaving, and turbo encoding.
- The multi-standard ConnX Turbo Decoder (ConnX Turbo16), a programmable turbo decoder for LTE and HSPA+ that achieves 150 Mbps decoded bit rate for LTE. The size of this multi-standard turbo decoder is in line with most RTL (register transfer level) hardware implementations in terms of power and area.

These Atlas dataplane processors offer superior performance per area and power for their specific operations, and are akin to hardware acceleration blocks that provide the post-silicon flexibility of a fully programmable processor. Coupled with the ConnX BBE16 DSP core, they offer leading class performance per area and power for a full LTE PHY implementation.