Debug platform upgrade enhances verification planning

Verdi Coverage enables users to understand project progress, manage regression data, launch verification jobs, track project trends, generate reports and ultimately optimise resource allocation.

Synopsys' innovative planning and coverage analysis technology is built on top of the Verdi environment recognised for being optimised, extensible and easy to use. Fully integrated with all Verdi debug views, it allows users to quickly analyse and cross-probe any holes identified through coverage analysis.

It is also interoperable across a wide range of solutions including simulation, static checking, formal verification, VIP and FPGA-based prototyping. This unique level of integration and interoperability provides a unified view of project status that allows users to focus only on tasks required to improve the predictability of verification closure.

"We have been collaborating closely with many SoC leaders on advanced planning and coverage technology, which is essential to effectively address the verification closure challenges of complex SoCs," said Yu-Chin Hsu, vice president of R&D in the Synopsys Verification Group. "We have made a significant investment in verification planning and coverage visualisation to address these challenges. Verification planning, coverage analysis and debug are fundamental elements of the Verification Compiler product, providing our customers with superior technology to help them meet their ever-shrinking schedules."