Synopsys unveils StarRC Custom parasitic extraction solution

Synopsys has announced its new StarRC Custom parasitic extraction solution for analogue mixed-signal (AMS) and custom digital IC design. By combining the gold standard Star-RCXT(TM) extraction technologies and the Raphael(TM) NXT 3D fast field solver into a single, unified extraction solution, the StarRC Custom solution offers high performance runtime with tuned accuracy to meet the analysis demands of high sensitivity custom circuits. This comprehensive offering includes optimised links with Synopsys’ technology leading CustomSim(TM) circuit simulator which can boost simulation runtime by up to 10X while preserving signoff accuracy. Additionally, StarRC Custom provides seamless integration with Synopsys’ Galaxy Custom Designer(TM) implementation solution to improve designer productivity.

“The widespread use of custom circuits in today’s complex system-on-chip (SoC) designs is creating a severe simulation and signoff bottleneck,” said Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys. “Increasing transistor count combined with the modeling of more complex parasitic effects is resulting in transistor-level simulation runtimes doubling and quadrupling. To address this challenge, Synopsys took a unique approach with StarRC Custom by focusing not only on extraction runtime and accuracy, but also on optimising the extraction data to improve overall transistor-level simulation throughput.”

StarRC Custom solution is built on the Star-RCXT gold standard technology and environment, enabling custom IC designers to get the instant benefit of Star-RCXT’s broadest qualification in the industry for 65nm and 45nm process nodes. Star-RCXT is already in use by more than 40 leading semiconductor companies at 45nm and trusted on more than 140 tapeouts at 16 foundries.

StarRC Custom provides the foundation of an expanded Synopsys extraction tools suite, which includes StarRC and StarRC Ultra. The next generation StarRC and StarRC Ultra solutions offer versatile solutions for full-chip, gate-level and transistor-level designs as well as technologies to support advanced analysis capabilities. The tools incorporate technologies such as hierarchical extraction, feature-scale chemical-mechanical polishing (CMP) effects modeling and variation-aware extraction to enable designers to achieve signoff accuracy while meeting their stringent tapeout schedules.