Synopsys Unveils DC Explorer for Early RTL Exploration

DC Explorer addresses this challenge by delivering 5X faster runtime and 10 percent timing and area correlation to DC Ultra™ RTL Synthesis. It also tolerates incomplete design data and therefore can be used very early in the design flow to guide the development of high-quality RTL and constraints, enabling a highly convergent design flow. These new productivity benefits DC Explorer delivers will be highlighted today by users at the Synopsys Users Group (SNUG™) meeting in San Jose, Calif.

Improving productivity at the early stages of design development can significantly accelerate our IC implementation flow, said Giancarlo Sada, deputy manager of the Digital Solutions and Pilot Projects team of Central CAD and Design Solutions organization at STMicroelectronics. We ran DC Explorer on multiple designs at various stages of development and have seen at least 4X faster runtime and 10 percent correlation to DC Ultra. This will enable our designers to efficiently assess various implementation alternatives early in the flow, tune the design data and create a highly convergent and faster design flow.

At the early RTL design development stages of today's large and complex ICs, the design data comes from multiple sources at varying levels of consistency and completeness. Engineers lack a fast and efficient way to explore and improve the data, fix design issues and create a better starting point for RTL synthesis that will lead to a highly convergent implementation flow. DC Explorer provides designers with the RTL exploration capabilities they need, helping them to efficiently identify potential design improvements and issues prior to implementation. In addition, when the input RTL, constraints and library models available are incomplete, DC Explorer generates comprehensive reports on what needs to be completed and fixed, speeding up the process of design creation. Lastly, script compatibility with Design Compiler® RTL Synthesis makes DC Explorer very easy to use and deploy into existing customer flows.

Synopsys is continuously focused on helping our customers improve their productivity and shorten design cycles for their Gigascale system-on-chip devices, said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. DC Explorer delivers the next significant productivity boost to IC designers, enabling them to perform RTL exploration very early in the design flow, improve the quality of their design data and significantly accelerate schedules.