Synopsys & UMC expand collaboration

The PQV provides additional silicon data, enabling UMC to further tune its 14nm FinFET process for optimal power, performance and area. This PQV follows the successful tapeout and silicon bring-up of the first UMC 14nm FinFET PQV containing Synopsys DesignWare Logic Libraries and utilising the StarRC parasitic extraction tool. 

"Our expanded collaboration with UMC demonstrates our mutual goal to help designers incorporate DesignWare IP into their SoCs on UMC processes," said John Koeter, Vice President of Marketing, IP and Prototyping, Synopsys. "With more than 45 FinFET test chip tapeouts, Synopsys continues to make significant investments in providing high-quality IP for FinFET processes, enabling designers to lower integration risk and speed their time to volume production."

"In addition to developing a competitive 14nm process for the most advanced IC applications, UMC is creating a highly comprehensive support infrastructure to accelerate the design-in process for 14nm customers," commented Steve Wang, Vice President, IP and Design Support division, UMC. "Following our success with Synopsys on the previous 14nm process qualification vehicle, this collaboration to bring Synopsys' high-quality DesignWare IP to our most advanced node will help our mutual customers realise additional power, performance and cost benefits."