Synopsys TetraMAX ATPG cuts test development schedule at Arrow Electronics

“To meet Arrow’s quality goals, our CLS ASIC designers rely on at-speed manufacturing tests that can take days to generate,” said Erich Van Stralen, ASIC test team manager at Arrow Electronics. “For our latest project, we used TetraMAX ATPG running on quad-core machines, which reduced test pattern generation time to less than 24 hours with no impact on fault coverage. We now consider the Synopsys multicore ATPG capability essential to meeting our quality goals on time.”

Generating deep-submicron tests on a single processor core can take weeks or longer, especially for very large designs. TetraMAX’s multicore processing capability employs algorithms to ensure that runtime performance scales well with the number of processor cores used, speeding ATPG runtime on eight cores, for example, by six times or more. Built into the Galaxy(TM) Implementation Platform to eliminate time-consuming iterations between synthesis, scan insertion and physical implementation, DFTMAX(TM) compression and TetraMAX ATPG provide designers with a comprehensive solution for meeting their most challenging quality and cost goals for test.

“Design engineers are under pressure to deliver increasingly complex products to market in less time but with higher quality,” said Gal Hasson, senior director of marketing for synthesis and test at Synopsys. “TetraMAX’s multicore processing capability accelerates test pattern generation, enabling customers, such as Arrow Electronics, to meet their test development schedules in the presence of increasingly challenging test requirements.”