Synopsys tapes out IP portfolio for TSMC 10nm FinFET process

Achieving this tape-out milestone enables designers to accelerate the development of SoCs that incorporate USB 3.1, USB 3.0, USB 2.0, HSIC, PCIe 3.0, PCIe 2.0 and MIPI D-PHY interface IP. In addition, Synopsys is developing embedded memories, DDR4, LPDDR4 and MIPI M-PHY IP, which will further extend its 10nm IP portfolio. TSMC's 10nm process provides 2.2 times the logic density, a 15% performance improvement, and 35% power reduction compared to their 16nm FinFET Plus process node. Taking advantage of the process, Synopsys has re-architected its IP at 10nm for lower power, higher performance and smaller area compared to the previous generation. As an example, the high-speed SerDes-based PHYs consume less than 5mW/Gb/lane. 

"As the leading provider of physical IP, Synopsys has collaborated with TSMC on the development of IP for the 10nm process, enabling designers to achieve the design goals of their next-generation SoCs," said John Koeter, Vice President of Marketing for IP and Prototyping, Synopsys. "By offering a broad portfolio of IP at the TSMC 10nm node, Synopsys is reducing the risks associated with moving to this new process technology."

"Synopsys' track record of providing high-quality IP through many generations of TSMC processes, including 10nm, offers designers a low-risk path to integrating high-performance IP into their SoCs," commented Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC. "Our close collaboration with Synopsys on the development of IP for the TSMC 10nm process enables our mutual customers to reduce their power and area, increase performance and accelerate their time to volume production."