Synopsys Speeds Equivalence Checking by 2X at Nuvoton

Time to market is critical to our business, said Chun-Ming Chang assistant vice president at Nuvoton. Formality delivered a 2X boost to our equivalence checking process and has helped us meet our critical tapeout schedule. It was easy to learn and use in our DC Ultra™ synthesis flow. We have standardized on Formality for all of our future designs.

Equivalence checking is performed throughout the design process, with failures often requiring multiple iterations that can take weeks to resolve. To accelerate the verification process, Formality is designed to work seamlessly with DC Ultra RTL synthesis, eliminating the need for the user to manually create complex setup files and bear the risk of erroneous verification. In addition, new technology in Formality is designed to analyze each failing point in a design and recommend step-by-step guidance to help the user quickly pinpoint and resolve issues saving many hours of manual debugging. Formality also includes an intuitive flow-based user interface to guide the user through the verification process, improving designer productivity and accelerating the time to successful verification.

Our customers are required to develop complex chips while reducing design schedules in order to stay competitive in the marketplace, said Ahsan Bootehsaz, vice president of engineering, design analysis and sign-off at Synopsys. We are committed to developing groundbreaking technologies in Formality that offer customers like Nuvoton the best turn-around-time for their most complex and highly optimized designs.