Open-Silicon selects Synopsys IC Compiler and achieves 1.3 GHz performance

We established the Center of Excellence for ARM based designs to provide our customers with complete ARM solutions from ARM sub-system design to power and performance-optimized processor hard macros, said Taher Madraswala, senior vice president of Engineering, Open-Silicon.



For performance optimization, we collaborated with Synopsys to leverage innovative technologies from the Galaxy Platform to enable the 1.3GHz frequency that our customers need to differentiate themselves in the market. As our leading-edge customers continue to push the power/performance envelope, we are confident that the winning combination of our design expertise and Synopsys tools and technologies will enable Open-Silicon to continue to deliver state-of-the-art ARM performance.



The quad-core processor targeted at a set-top box application was a sizeable design totaling more than three million instances with hundreds of macros, including four ARM NEON media processing engines. Implemented hierarchically, the design achieved a frequency of 1.3 GHz at the typical corner using 69 percent low-power long channel cells. Open-Silicon optimized the hard macro for a TSMC 40LP low-power process using ARM POP IP, comprised of standard cells and memories, as well as Synopsys' high-speed DesignWare Embedded Memories.



Many factors made timing closure a challenging task:

• Additional levels of logic were introduced by the complexity of the quad-core configuration

• The high cell density required for a compact core amplified timing sensitivity to placement, requiring tighter correlation between synthesis and place and route

• Top-level floorplanning required careful tuning to improve timing and area

• Performance was the highest priority, but leakage power also had to be managed

• The parts of the design related to memory access run at twice the processor clock speed (half clock cycle), further straining timing closure



The Open-Silicon design team created a flow with Design Compiler Graphical and IC Compiler that converged on timing quickly and predictably. They took full advantage of key capabilities such as:

• Design Compiler Graphical's physical guidance for 20 percent improved timing and 5 percent post-route correlation with IC Compiler

• IC Compiler's useful skew technology to close timing on the memory half cycle paths

• IC Compiler's final-stage leakage recovery that delivered a 5X reduction in the number of high power cells without impacting performance



Other Galaxy platform tools used in the quad-core implementation include Formality for equivalence checking as well as StarRC™ and PrimeTime® for signoff extraction and timing analysis.



Open-Silicon has a reputation for on-time delivery of complex SoC designs that meet performance and power targets and result in first-pass silicon success, said Dr. Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. Open Silicon's success in leveraging the differentiating technologies in Design Compiler and IC Compiler to predictably meet challenging design targets reinforces the position of the Galaxy Implementation Platform as the widespread choice for high-performance design.