Synopsys expands DesignWare IP portfolio with MIPI IP solutions

Leading providers of system-on-chips (SoCs) are adopting these standards to improve interoperability and reduce system cost for their next generation products. Synopsys has more than a decade of expertise in delivering high-speed interfaces, and its DigRF, CSI-2 and D-PHY solutions enable designers of baseband ICs and application processors to quickly integrate high quality MIPI interfaces into their complex SoCs with less risk.

MIPI DigRF v3 is a low-power, low pin-count interface that simplifies the integration and interoperability between the RF transceiver IC and baseband IC (BBIC). The six-pin digital interconnect reduces system cost and lowers Electromagnetic Interference (EMI) for dual and single-mode 3GPP 2.5/3G mobile terminals. The silicon-proven DesignWare 3G DigRF IP solution consisting of controllers, dual-mode PHY and verification environments is compliant with the latest standard specification and enables easy integration of the MIPI DigRF v3 standard in both digital baseband and RF ICs. The PHY includes an analogue phase-locked loop (PLL) and is developed as a hard IP block to help ensure the integrity of the high-speed clocks and signals required to meet the strict timing requirements of the protocol. Available in advanced 65 and 40nm process technologies, this high quality solution has been implemented in multiple baseband and RF IC designs.

“As a leading provider of open market ASIC solutions working with multiple foundries, sourcing high quality IP is key to our success,” said Shri Gokhale, chief operating officer at Open-Silicon. “The Synopsys DesignWare 3G DigRF IP enabled us to focus on our core competencies and successfully service our customer with a product that can easily interface with leading RF ICs in the market. As one of the first members of Synopsys’ IP OEM partner program, Open-Silicon is able to tightly integrate our engineers with the Synopsys IP engineering teams, allowing for a best-in-class IP integration experience for our customers.”

Implemented by leading phone manufacturers, camera sensor vendors and image processor suppliers, the MIPI CSI-2 specification provides an efficient low-power, low pin count interface between camera sensors and application processors. To meet the needs of a wide range of camera sensors ranging from economical low-end to the most demanding multi-megapixel cameras, the DesignWare CSI-2 Host Controller is configurable from one to four data lanes for a total throughput of up to 4 Gbps. Complementing the CSI-2 host controller is the DesignWare MIPI D-PHY, which is a fully-integrated hard macro available as a unidirectional or a bi-directional PHY. The unidirectional configuration is optimised to enable the implementation of very compact and low power CSI-2 host applications. The bi-directional configuration enables a single PHY to support multiple MIPI interfaces, greatly simplifying the development of designs implementing multiple MIPI interfaces such as CSI-2, DSI and UniPro. Delivering up to 1 Gbps per lane, the DesignWare MIPI D-PHY meets the bandwidth demands of today’s advanced cameras and display peripherals and is silicon-proven on 65nm and 40nm nodes.

“We are seeing an increasing momentum in the adoption of the MIPI Alliance interfaces standards,” said Joel Huloux, chairman of the board, MIPI Alliance, Inc. “Synopsys’ contribution to the different working groups and established position as a leading IP provider will help strengthen the MIPI ecosystem and further accelerate the adoption of the MIPI interfaces.”

“MIPI has become the de-facto industry standard for chip-to-chip interfaces within mobile terminals,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “With the addition of silicon-proven CSI-2, DigRF and D-PHY to the DesignWare IP portfolio, designers can now turn to a single, trusted vendor to help them successfully develop innovative mobile designs using MIPI interfaces with significantly less risk.”