Synopsys enables optimised high performance energy efficient ARM processor-based designs

Synopsys and ARM have collaborated in a series of implementation case studies across methodologies, libraries and process technologies targeted at increased performance of a fully automated synthesisable ARM Cortex-A8 processor. To achieve optimised results, the Synopsys team used the Synopsys Galaxy(TM) Implementation Platform, including some of the latest 2009.06 Design Compiler Graphical, IC Compiler, StarRC(TM) and PrimeTime(R) SI capabilities, ARM Physical IP libraries and memories for a 40nm foundry process together with highly tuned floorplan and design constraints. The ARM Cortex-A8 processor optimised implementation achieved greater than 2GHz in the typical corner on a 40nm process while consuming .24mW/MHz dynamic power and 57mW static power using less than 2% LVt cells.

The implementation team at Synopsys took advantage of the latest capabilities in the Galaxy Platform, including: library subset usage scenarios, delay performance versus cell area tradeoffs, cell placement density versus floorplan dimension tuning, leakage optimisation techniques, multi-corner multi-mode (MCMM) optimisation for better timing correlation and signoff optimisation between IC Compiler and Prime Time, as well as the usage of the latest clock tree synthesis capabilities together with intelligent user clock constraints. The Galaxy Platform is a key component of Synopsys' Eclypse(TM) Low Power Solution and the Lynx Design System.

Our collaboration with Synopsys will enable our licensees to achieve the kind of high performance they need while preserving energy efficiency to be competitive in their marketplace, said Eric Schorn, VP marketing, Processor Division, ARM. This optimised reference implementation methodology combined with ARM Physical IP will enable our partners to introduce more compelling ARM processor-based mobile and consumer products.

Synopsys is continuing to apply this optimised methodology used on the ARM Cortex-A8 processor to additional ARM Cortex processors. To learn about these optimised implementations, attend the ARM TechCon3 conference at the Santa Clara Convention Center, Santa Clara, Calif. on October 21-23 2009, where the Synopsys implementation team will present their latest ARM Cortex-A8 and ARM Cortex-A9 processor optimised implementation methodologies and results.

The latest results of our collaboration with ARM enable designers to take maximum advantage of the Galaxy Implementation Platform on designs using leading-edge ARM Cortex processor cores and Physical IP, said Dr. Antun Domic, senior vice president and general manager, Implementation group at Synopsys. By making this methodology available through the Lynx Design System, we will help customers to achieve the lowest cost of design and fastest time-to-market for their next generation mobile SoC designs.