Compression tool accelerates SoC design time

As a result, VIA Technologies has standardised on DFTMAX Ultra and TetraMAX for all pin-limited designs.

"DFTMAX Ultra delivered 11X higher compression on our pin-limited design, which allowed us to meet our manufacturing test goals," said JC Chen, design service manager of the Hardware Technology Development Center at VIA Technologies. "We were able to incorporate DFTMAX Ultra into our design flows within a few days without impacting our stringent schedules. Due to the superior results DFTMAX Ultra delivers, we will be using it for all our pin-limited designs."

Design teams are under pressure to ensure high manufacturing defect coverage while facing multiple factors that reduce the number of pins available for test. These include designs such as mobile applications that are pin-limited, large SoCs that have few pins per core for test access, as well as a technique known as multisite testing that checks for defects across multiple dies simultaneously. Companies like VIA Technologies are deploying DFTMAX Ultra to address the increased costs typically associated with pin-limited testing. By achieving significantly higher compression than previous technologies, DFTMAX Ultra enables high defect coverage utilising as few as one pair of test pins. Built into Design Compiler, DFTMAX Ultra synthesises the test compression logic into a design, then sets up Synopsys TetraMAX ATPG to generate high defect-coverage, power-aware test programs.

"A growing number of semiconductor companies, such as VIA Technologies, are adopting DFTMAX Ultra to aggressively cut test time and maintain high test quality," said Bijan Kiani, vice president of marketing for Synopsys' Design Group. "With innovative compression technology and value links to other products in the Synopsys Galaxy™ Design Platform, DFTMAX Ultra is helping our customers meet their most challenging design and test goals faster."