On-chip embedded flash test solution reduces design time

It is a built-in self-test (BIST) solution that tests for the failure mechanisms associated with embedded flash memories, reducing overall integration time and cutting associated test costs by 20 percent compared to external solutions. Embedded flash memories are increasingly used with microcontrollers in system-on-chips (SoCs) for Internet of Things (IoT) wearables, smart appliances and automotive safety systems, which have stringent cost and reliability requirements.

"Synopsys' DesignWare STAR Memory System for Embedded Flash is a valuable product for chip designers utilising our 55-nanometer process, which has already been widely adopted for numerous IoT applications," said Shih Chin Lin, senior director of IP development and design support division at UMC. "This solution provides our mutual customers with integrated test and repair capabilities that reduce overall design effort and lower test costs. Designers who are taking advantage of our 55-nanometer eFlash process will find that the post-silicon debug and analysis capabilities of Synopsys' Yield Accelerator and Silicon Browser will make designers' product characterisation and validation efforts even more efficient."

The system offers in-field diagnostic capabilities to identify issues during system operation. With these capabilities, memory issues can be diagnosed even after the devices have shipped to the end customer.

It allows hierarchical generation and verification of the test and repair IP to be inserted into the SoC while maintaining the original design hierarchy. This can reduce integration effort and SoC development time by allowing reuse of existing design constraints and configuration files.

Additionally, the post-silicon Yield Accelerator and Silicon Browser features can reduce the time required for silicon bring-up and defect analysis for yield optimisation, enabling the ramp to volume production to occur in weeks rather than months.