Synopsys DesignWare DDR multiPHY IP supports six DDR standards in a single PHY

“Memory interfaces continue to be one of the key IP requirements we see in chip development. New standards such as DDR3, DDR3L and LPDDR2 are designed to meet system performance requirements while utilising less power,” said Dr. Keh-Ching Huang, Head of Marketing and IP Solution Planning at Global Unichip. “By supporting all facets of the DDR standards, Synopsys’ unique DesignWare DDR multiPHY enables us to quickly incorporate the necessary functionalities into our SoC designs with less risk.”

The DesignWare DDR multiPHY is architected for extremely low power consumption and features Delay Lock Loop (DLL) bypass modes for operation below 200 MHz. It also features an I/O retention mode that allows the chip’s power supplies to be shut down completely while a small number of I/Os remain powered on to keep the external SDRAMs in self refresh mode. The DesignWare DDR multiPHY is designed to support the anticipated DDR3U standard operating at 1.2 or 1.25 V. Additionally, the DesignWare DDR multiPHY provides built-in data training circuits to enable in-system calibration, providing optimised system-level timing without material interaction with the memory controller.

The DDR multiPHY is a hard macro similar to Synopsys’ complementary DDR PHY offerings. Hard DDR PHYs offer significant benefits over “soft” PHYs or all digital PHYs such as:
- Quick integration. All pieces of the PHY come from one vendor and have been verified together
- Minimal timing closure problems. Known performance, proven in silicon
- Better performance margins. Lower jitter, better duty cycle and more supply noise rejection
- Area optimised circuits. Each bit path is designed with matched flight times on the data buses

“It has become as important to minimise power as it has to minimise overall chip cost in portable electronics,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “The DesignWare DDR multiPHY not only offers designers the flexibility to utilise any DDR SDRAM in the system through simple software control, it also features a power-conscious design that minimises the silicon area and cost.”

The DesignWare DDR multiPHY is a part of Synopsys’ comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and now LPDDR2. The comprehensive portfolio of DDR IP supports leading 130-nm, 90-nm, 65-nm, 55-nm and 45/40-nm technologies. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.