Synopsys DesignWare CXL IP supports AMBA CXS protocol

The DesignWare CXL Controller supports all the required CXL protocol types (.cache, .io, and .mem) and allows mixing multiple types within a single clock-cycle transfer for design flexibility. Support for CXS enables the extremely low-latency, high-bandwidth DesignWare CXL IP to extend its capabilities across Arm-based SoCs requiring cache coherency and fast chip-to-chip interconnects.

"The exponential growth in data creation, consumption, and processing is driving more cloud workloads to utilise domain specific acceleration, which demands a fast, efficient multichip interconnect to quickly move data," said Dermot O'Driscoll, Vice President of Product Management, Infrastructure Line of Business, Arm. "Our successful collaboration with Synopsys enables an optimised, ready-to-go CXL IP stack to meet the diverse multichip latency and bandwidth needs for a range of Arm-based server host and end-point solutions."

"High-performance computing applications such as AI accelerators, networking, and hyperscale data centres require coherent interfaces that enable high-speed, efficient communication between on- and off-chip protocols," added John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys. "By providing support for the AMBA CXS protocol, designers can easily interface Synopsys' DesignWare CXL IP to the Arm Coherent Mesh Network platform to meet the high-bandwidth requirements of their data-intensive Arm-based SoC designs."