Design
Synopsys Collaborates with Industry Consortium on Solutions to Model Latest 28-nm Parasitic Effects
Synopsys announced new extensions to its open source-licensed Interconnect Technology Format (ITF) which enables modeling of more complex device structures and interconnect layers for parasitic extraction tools at 28-nanometer (nm) and below process technologies. Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) to define these new extensions, which have been ratified by IMTAB members including Altera Corporation, AMD, Apache Design Solutions, GLOBALFOUNDRIES, LSI Corporation, Magma Design Automation, NVIDIA, Qualcomm, STMicroelectronics and Synopsys.
The new IMTAB ratified extensions to ITF include:
* Device conductor layer type specification to define a conductor's function based on the geometric characteristics
* High-k gate oxide thickness and dielectric constant specification for accurate capacitance calculation
* 2-dimensional table to model rectangular via etch as a function of length and width
* Area-dependent temperature coefficient table for accurate via resistance calculation
* Model format to describe through-silicon via (TSV) for on-chip extraction to support 3-dimensional IC and silicon interposer design methodologies
IMTAB members are collaborating to address real-world challenges facing the semiconductor industry in sub-28-nanometer process nodes, said Peter Lefkin, business development and marketing executive at IEEE-ISTO. The fast pace of innovation in the ITF modeling, as driven by IMTAB, will help the industry coalesce around a single proven format to improve tool interoperability and speed design flows, offering tremendous benefits to all.