Synopsys Announces Immediate Availability of Silicon-Proven DesignWare Data Converter IP in SMIC 65-nm LL Process Technology

The combination of Synopsys' silicon-proven DesignWare Data Converter IP and SMIC's low-leakage 65-nanometer process technology enables our mutual customers to meet their specific application requirements and integrate advanced functionality into their SoCs, said Chris Chi, Senior Vice President and Chief Business Officer of SMIC. Synopsys' strong application expertise in broadband wireless communications and digital TV make them a trusted IP provider and valued partner. As SMIC's business continues to expand, we look forward to further developing our synergistic relationship with Synopsys to meet the increasing requirements of our mutual customers.



The new DesignWare Data Converter IP solutions for the SMIC 65-nm LL process consist of a comprehensive portfolio of low power, compact ADCs and DACs for broadband wireless communications, including high-speed ADCs and DACs for the receive and transmit path as well as very efficient auxiliary converters for general purpose applications, including:



* 10-bit 80 MSPS Dual pipeline ADC

* 10/8-bit 2 MSPS SAR ADC with differential 8:1 input mux

* 12-bit 160 MSPS Current Steering IQDAC

* 11-bit 20 MSPS General Purpose DAC





These IP products offer a highly flexible analog interface that simplifies the connection between the digital SoC and the RFIC or other transceivers, eliminating the need for external components. These elements help designers reduce silicon costs and significantly simplify the integration of the IP into a SoC.



By working closely with SMIC to make the DesignWare Data Converter IP available in SMIC's 65-nanometer low leakage process, we continue to provide designers with the optimized IP they need for their specific applications in their required foundry processes, said John Koeter, senior vice president of marketing for IP and Systems at Synopsys. Achieving first-pass silicon success with our data converter IP demonstrates the robustness of Synopsys' design and verification processes as well as the scalability of the architectures, enabling designers using advanced process technologies to lower their integration risk and meet their time-to-market schedules.