Synopsys and CEVA Deliver Superior Performance, Power and Area for CEVA DSP Cores with DesignWare HPC Design Kit

The DesignWare HPC Design Kit is a suite of optimized high-speed and high-density memories and logic libraries that allow system-on-chip (SoC) designers to optimize their processor cores for maximum speed, smallest area, lowest power, or for an optimum balance of the three for their specific application. The CEVA-XC DSP architecture features a combination of VLIW (Very Long Instruction Word) and Vector engines that enhances typical DSP capabilities with advanced vector processing. The scalable CEVA-XC architecture offers a selection of highly powerful communication processors, with four generations to date (CEVA-XC321™, CEVA-XC323™, CEVA-XC4210™ and CEVA-XC4500™) widely licensed by leading vendors with over 20 design wins to date. The CEVA-XC architecture targets a broad range of communication applications and use cases including LTE-Advanced handsets, wireless infrastructure, Wi-Fi stations and access points, cable modem, satellite modem and more.

"DSPs are a key technology for today's fastest growing wireless and consumer electronic applications, and at CEVA we endeavor to meet our customers' design goals with DSPs optimized for power, performance and area to address their specific requirements," said Eran Briman, vice president of marketing at CEVA. "Our successful collaboration with Synopsys using their DesignWare HPC Design Kit has yielded impressive improvements in the performance and power of our CEVA-XC DSP cores, and is indicative of the efficiencies that this optimization process is capable of delivering across our portfolio of DSPs."

Synopsys' DesignWare HPC Design Kit is an add-on to the DesignWare Duet package of embedded memories and logic libraries. The Duet package contains all the physical IP elements needed to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimization Kits (POKs), as well as options for overdrive/low voltage process, voltage and temperature corners (PVTs), multi-channel cells and memory built-in self-test (BIST) and repair. The HPC Design Kit adds fast cache memory instances and performance-tuned flip-flops that enable speed improvement for processor cores of up to 10 percent over the standard Duet package. To minimize dynamic and leakage power as well as die area, the HPC design kit provides area-optimized and multi-bit flip-flops as well as an ultra-high density two-port register file, which reduces area and power by up to 25 percent while maintaining processor performance. Optimized design flow scripts and expert core implementation consulting services are also available to help design teams achieve their processor and SoC design goals in the shortest possible time.

"Physical IP elements including embedded memories and standard cell libraries are central to achieving the best performance, power and area results for DSP cores," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Our successful collaboration with CEVA to optimize their CEVA-XC DSP cores using Synopsys' DesignWare HPC Design Kit has resulted in substantial gains across the full speed, power and area spectrum, enabling designers to meet the design requirements of their target application.

The Synopsys DesignWare HPC Design Kit is available from Synopsys now, as is the CEVA-XC Family of DSPs.