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Synopsys allows Fuji Xerox to reduce silicon area by more than 50%

1st October 2015

Synopsys Inc

Siobhan O'Gorman

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Synopsys has announced Fuji Xerox used its ASIP Designer tool to design a high-performance Application-Specific Instruction Set Processor (ASIP) for its full-colour multifunction printer. With ASIP Designer, Fuji Xerox developed a specialised instruction-set custom processor that consumed less than 50% of the die area of a fixed hardware implementation while still meeting the performance requirements. In addition, unlike fixed hardware, an ASIP offers software programmability, providing the flexibility Fuji Xerox needed to meet the varied processing demands of its multifunction printer application. Using ASIP Designer, Fuji Xerox's design team was able to complete its ASIP design from concept to implementation in less than 14 months.

"Synopsys' reputation as the premier provider of ASIP development tools was the key factor in our decision to use ASIP Designer for our custom processor development," said Noriaki Tsuchiya, Manager of the Controller Development Group, Fuji Xerox. "ASIP Designer's rapid architectural exploration capability made it possible for us to immediately profile the architecture against our algorithms. Designing an ASIP with an instruction set and functional units tailored to our application domain enabled us to significantly reduce gate count, while achieving our required system performance of printing 70 pages per minute."

While angularity correction is typically done mechanically, the need for quiet operation in office automation equipment required Fuji Xerox to take the different approach of using advanced image processing algorithms to apply the correction to the scanned image. To implement this in a performance- and area-efficient way, with the flexibility to make modifications to the algorithm, Fuji Xerox chose to design a custom processor using Synopsys' ASIP Designer tool.

Synopsys' ASIP Designer allowed Fuji Xerox to use a high-level specification of the processor to quickly model multiple processor architectures. Using this single input specification, ASIP Designer automatically configured the Software Development Kit (SDK) containing an Instruction-Set Simulator (ISS), assembler, linker, debugger and C compiler, and also generated the synthesisable RTL design. The immediate availability of the C compiler and the ISS, including its advanced profiling capabilities, enabled the unique ‘compiler-in-the-loop’ methodology, allowing Fuji Xerox to rapidly profile the performance and tune the architecture for its specific image processing algorithms written in C.

"By replacing fixed hardware with ASIPs, companies like Fuji Xerox can significantly reduce total system cost, while increasing the overall flexibility of the design," commented John Koeter, Vice President of Marketing for IP and prototyping, Synopsys. "Fuji Xerox's implementation of an ASIP for image correction in their multi-function printer illustrates how Synopsys' ASIP Designer tool enables designers to rapidly explore and optimize processor architectures to achieve the best balance of programmability, performance and area, while accelerating the development of their SoC."