STMicroelectronics adopts IC comiler for CPU & GPU implementation

The switch to IC Compiler was enabled by best-in-class performance-centric technologies which repeatedly helped meet the very challenging performance, power and schedule targets.

"Over the years, ST and Synopsys have built many successes together, starting with the first 1 GHz dual-core CPU in 45nm technology and more recently with the 3 GHz dual-core version in 28nm FD-SOI technology in 2013," said Philippe Magarshack, executive vice president, Design Enablement and Services at STMicroelectronics. "IC Compiler reliably meets our performance and power needs and standardizing on it is a natural progression that allows us to collaborate closer on further technology advancements."

STMicroelectronics has a unique processor architecture made possible through their patented fully depleted Silicon on Insulator (FD-SOI) process technology.  An FD-SOI device can operate at significantly higher frequencies than an equivalent, traditional, bulk complementary-metal-oxide semiconductor (CMOS) device. It can also run very fast at low voltages, providing much higher energy efficiency. The close collaboration between STMicroelectronics design teams and Synopsys has led to a compelling implementation solution that fully exploits the performance and power promise of FD-SOI technology and provides the throughput needed to meet tight time to market windows. STMicroelectronics' processor implementation kit utilizes several key technologies from the Synopsys Galaxy™ Implementation Platform, including:

• Design Compiler^® Graphical physical guidance tool for improved place and route correlation
• IC Compiler concurrent clock, data, and layer-aware optimization to boost performance
• IC Compiler physical datapath for the structured placement of registers and memories to meet timing
• Hierarchical flow with innovative one-pass budgeting for shorter turnaround time
• PrimeTime^® physical-aware ECO guidance technology with IC Compiler minimum physical impact implementation for faster ECO closure
• In-Design physical verification with IC Validator for faster DRC convergence
• Multivoltage design with IEEE 1801 UPF standard that spans the entire Galaxy flow to support complex low power management strategies

"We appreciate that a semiconductor leader like ST has access to many choices. It is therefore highly gratifying to have them standardize on IC Compiler," said Antun Domic, executive vice president and general manager, Implementation Group at Synopsys. "We view this as a strong vote of confidence in our technology direction and look forward to coming years of collaboration to drive even higher levels of design efficiency."