SpringSoft and Synopsys Link Debug Technologies to Speed Protocol Verification for SoC Designs

As leading system-on-chip (SoC) designs incorporate multiple complex protocols, verification IP (VIP) has become a critical component of the verification environment, enabling engineers to reach their coverage goals within tight project schedules. With the increase in protocol complexity, protocol debug is now one of the most difficult and time-consuming aspects of SoC functional verification. This collaboration, implemented with SpringSoft's VIA (Verdi Interoperability Apps) platform, directly addresses these challenges by combining the protocol-centric debug capabilities in Protocol Analyzer with the advanced design debug capabilities of the Verdi system.

Protocol debug poses a significant challenge for SoC design teams, said Mark Milligan, vice president of corporate marketing at SpringSoft. We have had a long-term partnership with Synopsys to jointly address the verification challenges of our mutual customers with interoperable tools and flows. The VIA-enabled integration of Verdi, the industry's de facto standard debug platform, and the advantages of Synopsys' Discovery VIP provide a compelling solution to speed protocol debug.
As protocol complexity has increased, efficient protocol debug has become an area of concern for the industry, said Janick Bergeron, verification fellow at Synopsys. Addressing the protocol debug challenge was one of our key areas of focus when developing our next-generation VIP. With this collaboration, our protocol debug technology is integrated with SpringSoft's market-leading design debug technology to further enhance SoC verification productivity.

Verification engineers use VIP to test all SoC interface protocols, including ARM® AMBA® AXI4™, USB 3.0, PCI Express, and others. Protocol Analyzer, available with the Synopsys Discovery VIP family, provides protocol-centric debug and unique capabilities that enable engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior by minimizing unnecessary detail and focusing on high-level protocol activity such as AXI transactions, USB transfers or PCI Express packets. The Verdi Automated Debug System, the cornerstone of SpringSoft's family of functional closure products, accelerates the process of finding, analyzing and correcting the root causes of errors revealed during the verification of complex digital IP components, design modules or entire SoCs.
The integrated flow between Protocol Analyzer and Verdi provides seamless and synchronized access between protocol transactions, transfers, packets and signal-level analysis of the design. This enables verification engineers to work at the most relevant level to determine the root cause of protocol violations and thereby speed the overall SoC debug process.