Sondrel accelerates SoC design with Synopsys

As Sondrel expands its capabilities to transform designs into tested, volume-packaged silicon, Synopsys was chosen based on several critical benchmarks to replace its legacy design systems. Synopsys' track-record of power-efficient designs and power, performance and area metrics drove Sondrel's decision to adopt the design and verification technologies enabling power-efficient SoC designs with the best quality-of-results (QoR) and time-to-results.

"Customers come to Sondrel for solutions that push the boundaries," said Graham Curren, Sondrel's CEO and Founder. "Every year, SoCs become larger and more complex. Our reputation is built on delivering these leading-edge designs on time and on budget. And, to do that, we need the best-in-class tools such as the Synopsys comprehensive digital and verification full-flow solutions. We have collaborated closely with Synopsys for many years and they are a trusted partner who always goes the extra mile to help us exceed our customers' expectation."

Sondrel plans to use Synopsys' design and verification platform solutions to enable the creation of some of the most complex and power-efficient architectures for their customers. Sondrel's focus on the design of large digital multi-core complex fabrics stems from decades of extensive expertise configuring leading processor architectures and targeting advanced process nodes from leading foundries.

"Through our collaboration, Sondrel's customers can leverage Synopsys' platform solutions to design and verify complex, power-efficient SoCs for various markets," said Sanjay Bali, Vice President of Product Marketing at Synopsys. "Sondrel can confidently achieve product differentiation and the highest level of productivity utilising Synopsys comprehensive design and verification solutions for its designs."

The Synopsys Fusion Design Platform solutions and features include:

• Fusion Compiler RTL-to-GDSII implementation system.
• IC Compiler II place-and-route solution with machine-learning technologies.
• Design Compiler NXT leading synthesis solution for advanced nodes.
• IC Validator physical signoff delivering cloud-optimised physical signoff including DRC, LVS, PERC and Fill.
• PrimeTime golden timing signoff solution.
• PrimePower for RTL to signoff power analysis.
• StarRC golden signoff parasitic extraction solution.
• TestMAX DFT provides comprehensive advanced design-for-test solution across a range of complexities.
• Formality equivalence checking for rapidly growing chip functionality and best verifiable QoR.

The Verification Continuum platform enables Sondrel to perform scalable SoC verification, including:

• Platform Architect Ultra for early SoC architecture analysis and optimization.
• VCS simulation with native low power simulation for mixed language RTL and gate level with the smallest memory footprint.
• Industry de facto standard Verdi advanced debug solution.
• Verification IP for emerging titles.
• VC SpyGlass for RTL signoff and VC LP for static low power signoff.