Software speeds time to first prototype by 3X

ProtoCompiler enables designers to quickly compile RTL and then generate a multi-FPGA design partition in a matter of minutes, versus hours for an existing design flow. ProtoCompiler's high-capacity logic synthesis and partitioning features automatically generate a high-performance, cycle-accurate design representation that operates seamlessly across multiple FPGAs. The flow to convert ASIC RTL to HAPS multi-FPGA flexible architecture has been accelerated with multi-threaded processing, an optimized, faster compiler and ASIC gated clock-conversion methods tailored for the HAPS Series.

"Synopsys' HAPS FPGA-based prototyping is invaluable for accelerating hardware/software validation, helping us deliver our new OWL series tablet SoCs with higher quality and in less time," said Mu Wu, deputy manager, system verify department at Actions Semiconductor. "We are excited by the announcement of Synopsys' ProtoCompiler software, which will transform prototyping by providing automation and debug tools that have intimate knowledge of HAPS systems. This enables designers to achieve faster time to results with higher performance prototypes."

ProtoCompiler understands the HAPS hardware interconnect architecture and detailed trace delay timing information to enable automated multiplexing. The new tool capabilities combined with HAPS high-speed time-domain multiplexing (HSTDM) and Synopsys' HapsTrak® connectors enable an increased average of 2X system performance when compared to other solutions.

"The combination of Synopsys' ProtoCompiler software and Xilinx® Vivado® Design Suite's next-generation analytical place and route technology provides maximum productivity for design teams who prototype SoC designs with Synopsys HAPS and the Xilinx Virtex-7 FPGA family," said Tom Feist, senior marketing director of design methodology at Xilinx. "Designers using FPGAs for ASIC and SoC prototyping require rapid system bring-up and high-performance implementations, and ProtoCompiler's design automation and debug delivers on both of these requirements."

ProtoCompiler provides a range of design visibility features including simulator-like RTL debug, automated connection to logic analyzers, full visibility with Synopsys' Siloti® visibility automation technology and superior debug and analysis with the Synopsys Verdi3™ automated debug environment to troubleshoot tasks throughout the prototype's lifecycle. Greater visibility into a multi-FPGA HAPS system is enabled by RTL instrumentation, gigabytes of sample trace storage and a non-invasive approach to the prototype-to-workstation connection that does not consume general purpose FPGA I/Os. Gigabyte storage options provide full seconds of debug visibility essential for the validation of complex hardware/software interactions. ProtoCompiler debug capabilities also integrate with the functional verification capabilities of Synopsys' Verification Compiler™ flow to deliver comprehensive visualization across static, formal, simulation, VIP, emulation and prototyping.

"Prototype designers have a short period of time between the 'RTL-drop' and delivery of an operational prototype for hardware/software integration. ProtoCompiler's HAPS-aware capabilities enable developers to accelerate their time to first prototype, while providing significant debug capacity and high system performance," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "Our integrated hardware/software solution using ProtoCompiler and HAPS gets prototypers up and running much faster and with better results than traditional methods."

ProtoCompiler software is available now and compatible with HAPS-DX and HAPS-70 Series systems. A variant of ProtoCompiler, ProtoCompiler DX, is included with all HAPS-DX systems.