RTL synthesis solution reduces design area by 10%

29th September 2014

Synopsys Inc

Siobhan O'Gorman

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Synopsys have announced that a number of customers using it's Design Compiler RTL synthesis solution have achieved smaller design areas. To reduce system costs or incorporate additional functionality without increasing die size, area optimisation is particularly important for designers across a wide range of electronic applications.

The RTL synthesis solution, part of the company's Galaxy Design Platform, features advanced optimisations which operate on new or legacy design netlists with and without physical information. This lowers power and allows the creation of smaller, more routable designs without impacting timing. According to the company, while maintaining quality of results, the Design Complier reduces design area and leakage power by an average of 10%. The solution also features RTL analyses and cross probing capabilities which speed up design schedules.

"Minimising area and meeting timing requirements enables us to differentiate and deliver value in a highly competitive multi-functional product marketplace," said Michihiro Okada, General Manager of the Software 3 R&D Division, Corporate Software Development Division at KYOCERA Document Solutions. "Design Compiler's new monotonic area optimisation reduced design area by 10% for multiple designs while meeting timing requirements and lowering leakage power. This allowed my design team to implement additional functionality without an increase in die cost."

"As a leader in mixed-signal semiconductors for the automotive, industrial and consumer markets, reducing die size is critical to meeting our business objectives," said Armin Kemna, Director Design Support at Elmos Semiconductor. "We are seeing up to 10% reduction in gate count simply by using the latest release of Design Compiler. In addition, technology links between Design Compiler and IC Compiler provided early insight into physical challenges and helped us stay on schedule."

"Smaller die size and shorter design schedules continue to be key requirements for our customers designing at both established and emerging process nodes," said Bijan Kiani, Vice President of Marketing for Synopsys' Design Group. "These new technologies for smaller area and lower power consumption help our customers to be more competitive in their market segments, while strengthening Design Compiler's position as the synthesis tool of choice for designers worldwide."